1. Field of the Invention
The present invention relates to circuits. More specifically, an output buffer or transceiver circuit having a variable impedance output is disclosed.
2. Description of the Prior Art
In integrated circuits, such as microprocessors, memories, transceivers, and the like, signals may be routed for relatively long distances using transmission lines. A transmission line may be a bus, a printed circuit board trace, or another type of relatively long metal line for transporting a signal. Typically, a printed circuit board trace has a characteristic impedance of between 50 and 75 ohms. The receiving end of the far end of the transmission line is typically connected to an input of a logic or receiver circuit where input impedance may not match the characteristic impedance of the transmission line. If this mismatch exists, the signal may be reflected back to the sending end, causing a ringing effect of overshoot and undershoot. This ringing effect degrades noise immunity and increases time for the signal to become, and remain, valid at the far end.
An impedance matching circuit is disclosed in U.S. Pat. No. 5,606,275, included herein by reference, where an external resistor 32 is used and the output impedance is adjusted by converting a sensed voltage level across the external resistor 32 into a digital code using analog-to-digital converters 22 and 24 as shown in FIG. 1. The A/D converters 22 and 24 include comparators 42 and 44 for providing digital signals to binary counters 48 and 51. The binary counters 48 and 51 count up or down in response to the digital signal from the comparators 42 and 44 to adjust a resistance of binary weighted transistor arrays 45 and 46 to match the resistance of the external
These binary counters 48 and 51 increase or decrease by 1 least significant bit (LSB) for each cycle, making the period of impedance adjustment too long. A worst-case example using an 8-bit counter of U.S. Pat. No. 5,606,275 would require 2{circumflex over ( )}8 or 256 clock cycles to correctly match the resistance of the external resistor 32.
It is therefore a primary objective of the claimed invention to disclose a new counter that can greatly shorten the impedance adjustment process.
Briefly summarized, the claimed invention discloses a selection circuit as a counter that includes a plurality of latch circuits each connected to one of a plurality of logic circuits. Each latch circuit has a first input commonly connected to a signal line IN that indicates whether an input voltage is to be raised or lowered and a second input connected to one of a plurality of non-overlapping digital clock signals.
Each of the logic circuits is structurally different but each logic circuit inputs a latched value of IN from the corresponding latch circuit and at least one of the digital clock signals. The selection circuit outputs a control signal to adjust an input voltage to match a reference voltage using a plurality of first control lines, each first control line indicating one bit in the 3-bit digital control signal.
Initially, the invention selection circuit outputs a code that generates approximately half of the maximum output resistance. If the resistance generated by this code is greater than an external resistor, a value of xe2x80x9c0xe2x80x9d will be latched by a latch circuit corresponding to the most significant bit of the control signal, otherwise a value of xe2x80x9c1xe2x80x9d will be latched by the same latch circuit, effectively halving the possible voltage range. At the falling edge of the next digital clock signal, a next latch circuit latches the second most significant bit of the control signal similarly, having again the possible voltage range. A third digital clock signal latches the third most significant bit of the control signal, ending the impedance matching process for that cycle.
The selection circuit of the present invention can easily be extended to function with a control line of N bits by including N latch circuits and N logic circuits. Each successively added logic circuit M (1 less than M less than =N) would comprise an AND operator receiving the latched value from the corresponding latch circuit M and the inverted corresponding digital clock signal CLKM. The result of the AND operator would be inputted into an OR operator that also inputs all of the digital clock signals CLK1 to CLK[Mxe2x88x921]. For example, a fourth logic circuit 280 (not shown) would apply an AND operator to an inverted digital clock signal CLK4 (not shown) and a latched value from a latch circuit 240 (not shown) that receives the signal line IN and the digital clock signal CLK4. The result of the AND operation would be an input into an OR operator along with the digital clock signals CLK1 to CLK3. The result of the OR operation would be outputted via a first control line GI4 (not shown)and would represent the 4th most significant digit in the control signal.
A useful application of the claimed selection circuit is as a replacement for a counter in a buffer circuit. The control signal outputted from the selection circuit controls a binary weighted transistor array that can adjust an input voltage. This adjusted input voltage is compared with a predetermined reference voltage and the result of the comparison is fed to the selection circuit. An output signal from the selection circuit goes to an output register where the output signal is used to control an output driver.
It is an advantage of the claimed invention that the selection circuit can complete the impedance matching process for an 8-bit control signal in only 8 clock cycles, requiring only one clock cycle for each bit in the control signal. This increased speed is evident every time there is more than the smallest impedance mismatching. Furthermore, the claimed selection circuit can be used with existing impedance matching circuits without requiring major redesigning complications or costs.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.